Ongoing
Design and development of an EEG-based real-time Depth of Anaesthesia (DoA) monitoring system
- Sponsor
- Ministry of Electronics and Information Technology (MeitY), Govt. of India
- Role
- Co-Principal Investigator
Research
Externally Funded Projects
Ongoing/ Completed Projects as Chief Investigator (CI)/ Principal Investigator(PI)/ Co-CI/ Co-PI
Research interests
- Approximate computing
- Digital VLSI design
- Computer arithmetic
- Energy-efficient hardware for machine learning
- Low-power biomedical ASICs
- EEG signal processing
- Design for testability (DFT)
- FPGA-based system design
Funded projects
Research themes
Error-aware approximate arithmetic
Arithmetic units dominate the area and energy of signal-processing and learning hardware. I develop error-aware design procedures for approximate multipliers, squarers, square-root circuits and logarithmic/antilogarithmic converters, so that a designer can pick a hardware configuration that meets a guaranteed worst-case error.
Key papers: IEEE TCAS-II 2020, Microelectronics Journal 2019, CSSP 2019, Integration 2026
VLSI architectures for machine learning
My doctoral work, “Approximate Computing Based VLSI Design for Energy-Efficient Cascade Support Vector Machine”, produced a hardware-efficient cascade SVM with on-chip training and classification. Related work covers energy-efficient k-means clustering hardware and pseudorandom bit generators.
Key papers: CSSP 2020, MNDCS 2021
Biomedical signal processing and electronics
Towards a real-time monitor of a patient’s depth of anaesthesia, I work with students and collaborators on EEG features and machine-learning models for depth-of-anaesthesia estimation, deep-learning methods for removing ocular and muscular artifacts from EEG, and low-power hardware to run them.
Key papers: Med. Biol. Eng. Comput. 2026, ICNGCS 2025, ICCEDT 2023